Self-analyzing memory words are a type of CAM or Content-addressable memory (US Patent Classification 365/49, Associative memories), and 711/108, Content addressable memory (CAM). Self-analyzing memory words can be constructed using a combination of CMOS pass transistor logic (326/113, Transmission gate logic) and CMOS logic (326/121, CMOS). Circuits are of the charge recovery type, that is, approximately adiabatic; they use pulsating power supplies with differing phases (326/96, Two or more clocks). Self-analyzing memory words are intended for massively parallel processing (708/507, Electrical digital calculating computer, parallel).
Content-addressable memory is well suited to the quick look up of an item in an unstructured table but it is poorly suited as a general purpose computer. Prior CAM depends on a global bus, so it suffers a major slowdown when there are multiple items to be read, modified, and re-written. Prior CAM art includes Lattibeaudiere, U.S. Pat. No. 5,438,535, 1995. Here each selected item must be prioritized, and then be read out using a global bus for this purpose. Unfortunately, bus usage is slow and dissipative of power, particularly when there are a very large number of selections. Thus it is impractical to perform parallel processing in which every word in memory is modified for every step of a given task.
Self-analyzing memory words use approximately adiabatic, logically reversible circuits. Prior art in logically reversible, approximately adiabatic logic applies, for example, to a fill adder, which is quite different from a CAM. Prior art includes switching between a forward and a reverse logic circuit, also quite different from the toggle-on/toggle-off memory cell approach of this disclosure.